mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1199

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Port data logic applies to the general purpose input/output function, which is the default
function for a port pin when no shared on-chip module is enabled and the pin interrupt
function is disabled.
Each port has a data register, a data direction register, and a pin value register. Besides
the EGPIO pin interrupt function, an I/O port bit may or may not share an I/O pin with
another on-chip module. Consult the Signal Multiplexing description for information
about pin assignments.
46.4.1.1 Operation when EGPIO controls pin
If the pin interrupt for a pin is not enabled (the PTIPE bit is 0), the direction of the pin
depends on the associated PTDD bit. When the PTDD bit is 1, data written to the port
data (D) register is driven out to the corresponding pad.
If the pin interrupt for a pin is enabled (the PTIPE bit is 1), the direction of the pin is
configured as an input and the associated PTDD bit has no effect. In this case, data
written to the port data (D) register is not driven out to the corresponding pad. When the
associated PTDD bit is cleared, a read of the port data register returns the logic level of
the associated pin. When the PTDD bit is set, a read of the port data register returns the
last value written to the associated bit of the port data register.
Freescale Semiconductor, Inc.
Read xDD
Write xDD
Write xD
Read xPV
Read xD
Figure 46-79. Diagram of port data logic function
MCF51JF128 Reference Manual, Rev. 2, 03/2011
PTDD[n]
PTD[n]
Preliminary
1
0
Synchronizer
Chapter 46 Enhanced GPIO (EGPIO)
Output Enable
Port Data Out
Port Data In
1199