mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1288

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
If a host is attempting to communicate with a target MCU that has an unknown BDC
clock rate, a SYNC command may be sent to the target MCU to request a timed
synchronization response signal from which the host can determine the correct
communication speed. After establishing communications, the host can read XCSR and
write the clock switch (CLKSW) control bit to change the source of the BDC clock for
further serial communications if necessary.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup
resistor is required. Unlike typical open-drain pins, the external RC time constant on this
pin, which is influenced by external capacitance, plays almost no role in signal rise time.
The custom protocol provides for brief, actively driven speed-up pulses to force rapid rise
times on this pin without risking harmful drive level conflicts. Refer to
BDM
Communication
Details, for more details.
When no debugger pod is connected to the standard 6-pin BDM interface connector
(Freescale-Recommended BDM
Pinout), the internal pullup on BKGD chooses normal
operating mode. When a development system is connected, it can pull BKGD and
RESET low, release RESET to select active background (halt) mode rather than normal
operating mode, and then release BKGD. It is not necessary to reset the target MCU to
communicate with it through the background debug interface. There is also a mechanism
to generate a reset event in response to setting CSR2[BDFR].
50.4.1.3 BDM Communication Details
The BDC serial interface requires the external host controller to generate a falling edge
on the BKGD pin to indicate the start of each bit time. The external controller provides
this falling edge whether data is transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven by an external controller or by the
MCU. Data is transferred msb first at 16 BDC clock cycles per bit (nominal speed). The
interface times-out if 512 BDC clock cycles occur between falling edges from the host. If
a time-out occurs, the status of any command in progress must be determined before new
commands can be sent from the host. To check the status of the command, follow the
steps detailed in the bit description of XCSR[CSTAT].
The custom serial protocol requires the debug pod to know the target BDC
communication clock speed. The clock switch (CLKSW) control bit in the XCSR[31–24]
register allows you to select the BDC clock source. The BDC clock source can be the bus
clock or the alternate BDC clock source. When the MCU is reset in normal user mode,
CLKSW is cleared and that selects the alternate clock source. This clock source is a fixed
frequency independent of the bus frequency so it does change if the user modifies clock
generator settings. This is the preferred clock source for general debugging.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
1288
Freescale Semiconductor, Inc.