mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 71

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
FlexNVM
FlexRAM
RAM
Total random access memory (RAM)
FlexMemory (FlexNVM plus FlexRAM)
configuration examples
Low-leakage standby memory
External bus interface (Mini-FlexBus)
Serial programming interface (EzPort)
External crystal oscillator or resonator
External clock
Internal clock references
Phase-locked loop (PLL)
Frequency-locked loop (FLL)
Random number generator (RNGB)
Cryptographic Acceleration Unit (CAU)
Feature
1
Table 2-1. Feature Summary (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Up to 32 KB
Up to 2 KB
Up to 32 KB
Up to 34 KB (32 KB + 2 KB)
Example 1: 32 KB additional program flash, no data flash or EEPROM, 2 KB
additional RAM
Example 2: 32 KB data flash memory, 2 KB additional RAM
Example 3: Up to 2 KB high-endurance, nonvolatile, enhanced EEPROM
Example 4: Partial data flash and EEPROM
Full RAM in LLS and VLLS3 power modes, 1 KB RAM or 8KB RAM in VLLS2
mode
32-byte register file in all power modes, including VLLS1 mode
Supports glueless connections to external memories and peripherals
Up to 20 address and 8 data lines (non-muxed mode)
Up to 20 address lines and 16 data lines (muxed mode)
2 chip selects
Supports flash in-system programming
Low range, low power, or full-swing: 32 kHz to 40 kHz
Medium range, low power, or full-swing: 2 MHz to 8 MHz
High range, low power, or full-swing: 8 MHz to 32 MHz
DC to 50 MHz
Two internal trimmable reference clocks
Internal 1 kHz low power oscillator
Up to 100 MHz VCO
1
Supports both true (TRNG) and pseudo-random number (PRNG) generators
Provides hardware encryption for:
Enables more complex algorithms such as 3DES with software encryption
libraries that use the preceding basic security blocks
Table continues on the next page...
System Security and Integrity
• 32 kHz
• 2 MHz
• DES
• AES-128, AES-192, AES-256
• SHA-1 and SHA-256
• MD5
Preliminary
Clocks
Details
Chapter 2 Introduction
71