mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 391

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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1. If debug is enabled, the core clock remains to support debug.
17.4.2 Power Mode Entry/Exit Sequencing
When entering or exiting low power modes, the system must conform to an orderly
sequence to manage transitions safely. The SMC manages the system's entry to and exit
from all power modes. The following diagram illustrates the connections of the SMC
with other system components in the chip that are necessary to sequence the system
through all power modes.
Freescale Semiconductor, Inc.
Transition #
10
11
9
Table 17-7. Power mode transition triggers (continued)
VLPR
VLPR
From
RUN
LLS
MCF51JF128 Reference Manual, Rev. 2, 03/2011
VLLS(3,2,1)
RUN
LLS
LLS
To
Preliminary
PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
VLLSCTRL[VLLSM]=001(VLLS1) or 010 (VLLS2) or 011
(VLLS3), STOPE=1, WAITE=0
Issue STOP instruction.
PMPROT[ALLS]=1, PMCTRL[STOPM]=011, STOPE=1,
WAITE=0
Issue STOP instruction.
Wakeup from enabled LLWU input source or RESET pin
PMPROT[ALLS]=1, PMCTRL[STOPM]=011, STOPE=1,
WAITE=0
Issue STOP instruction.
Trigger Conditions
Chapter 17 System Mode Controller (SMC)
391

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