mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 913

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.3.2 SPI control register 2 (SPIx_C2)
This read/write register is used to control optional features of the SPI system.
Addresses: SPI0_C2 is FFFF_81A0h base + 1h offset = FFFF_81A1h, SPI1_C2 is FFFF_81B0h base + 1h offset = FFFF_81B1h
Freescale Semiconductor, Inc.
SPIMODE
MODFEN
TXDMAE
BIDIROE
SPMIE
Reset
Field
Read
Write
7
6
5
4
3
Bit
SPMIE
SPI match interrupt enable
This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function.
0
1
SPI 8-bit or 16-bit mode
This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length. In master mode, a
change of this bit aborts a transmission in progress, forces the SPI system into an idle state, and resets
all status bits in the S register. Refer to the description of “Data Transmission Length” for details.
0
1
Transmit DMA enable
This is the enable bit for a transmit DMA request. When this bit is set to 1, a transmit DMA request is
asserted when both SPTEF and SPE are set, and the interrupt from SPTEF is disabled.
0
1
Master mode-fault function enable
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave
select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the
description of the SSOE bit in the C1 register.
0
1
Bidirectional mode output enable
When bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to 1, the BIDIROE bit
determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or
effect.
7
0
Interrupts from SPMF inhibited (use polling)
When SPMF is 1, requests a hardware interrupt
8-bit SPI shift register, match register, and buffers
16-bit SPI shift register, match register, and buffers
DMA request for transmit is disabled and interrupt from SPTEF is allowed
DMA request for transmit is enabled and interrupt from SPTEF is disabled
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
SPIMODE
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_C2 field descriptions
TXDMAE
Table continues on the next page...
0
5
Preliminary
MODFEN
0
4
Description
BIDIROE
0
3
Chapter 38 Serial Peripheral Interface (SPI)
RXDMAE
0
2
SPISWAI
0
1
SPC0
0
0
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