mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 920

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Register Definition
In 16-bit mode, reading either byte (the DH or DL register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the DH or DL register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
Addresses: SPI0_DL is FFFF_81A0h base + 5h offset = FFFF_81A5h, SPI1_DL is FFFF_81B0h base + 5h offset = FFFF_81B5h
38.3.7 SPI match register high (SPIx_MH)
Refer to the description of the ML register.
Addresses: SPI0_MH is FFFF_81A0h base + 6h offset = FFFF_81A6h, SPI1_MH is FFFF_81B0h base + 6h offset = FFFF_81B6h
38.3.8 SPI match register low (SPIx_ML)
This register, together with the MH register, contains the hardware compare value. When
the value received in the SPI receive data buffer equals this hardware compare value, the
SPI match flag (SPMF) sets.
In 8-bit mode, only the ML register is available. Reads of the MH register return all
zeros. Writes to the MH register are ignored.
920
Bits[15:8]
Bits[7:0]
Reset
Field
Reset
Field
Read
7–0
Read
7–0
Write
Write
Bit
Bit
Data (low byte)
Hardware compare value (high byte)
7
0
7
0
0
0
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_MH field descriptions
SPI0_DL field descriptions
0
0
5
5
Preliminary
0
0
4
4
Bits[15:8]
Bits[7:0]
Description
Description
0
0
3
3
0
0
2
2
Freescale Semiconductor, Inc.
0
0
1
1
0
0
0
0