mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 440

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
1. A value for FCTRIM is loaded during reset from a factory programmed location .
2. A value for SCFTRIM is loaded during reset from a factory programmed location.
20.3.5 MCG Control 5 Register (MCG_C5)
Address: MCG_C5 is FFFF_8400h base + 4h offset = FFFF_8404h
440
PLLCLKEN
SCFTRIM
PLLSTEN
Reserved
FCTRIM
Field
Reset
Field
4–1
Read
Write
0
7
6
5
Bit
10
11
Fast Internal Reference Clock Trim Setting
FCTRIM
clock period. The FCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
Increasing the binary value increases the period, and decreasing the value decreases the period.
If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that
value from the nonvolatile memory location to this register.
Slow Internal Reference Clock Fine Trim
SCFTRIM
SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount
possible.
If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this bit.
This read-only bit is reserved and always has the value zero.
PLL Clock Enable
Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV
needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4
MHz range prior to setting the PLLCLKEN bit). Setting PLLCLKEN will enable the external oscillator if not
already enabled. Check for OSCINIT assertion while enabling the external oscillator after being turned off.
0
1
PLL Stop Enable
7
0
0
MCGPLLCLK is inactive.
MCGPLLCLK is active.
Encoding 2 — Mid-high range.
Encoding 3 — High range.
1
PLLCLKEN
controls the fast internal reference clock frequency by controlling the fast internal reference
2
controls the smallest adjustment of the slow internal reference clock frequency. Setting
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
MCG_C4 field descriptions (continued)
PLLSTEN
MCG_C5 field descriptions
Table continues on the next page...
0
5
Preliminary
0
4
Description
Description
0
3
PRDIV
0
2
Freescale Semiconductor, Inc.
0
1
0
0