mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 274

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
12.2.1 MAC Status Register (MACSR)
The MAC status register (MACSR) contains a 4-bit operational mode field and condition
flags. Operational mode bits control whether operands are signed or unsigned and
whether they are treated as integers or fractions. These bits also control the overflow/
saturation mode and the way in which rounding is performed. Negative, zero, and
multiple overflow condition flags are also provided.
274
31–12
PAVn
OMC
Reset
Reset
11–8
BDM:
Field
7
W
W
R
R
31
15
0
0
0
0
Reserved, must be cleared.
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms
the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l,
MACSR instruction or the accumulator is loaded directly.
Bit 11: Accumulator 3 . . .
Bit 8: Accumulator 0
Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set
to the appropriate constant (see S/U field description) on any operation that overflows the accumulator.
After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the
overflow bit is cleared or the accumulator is directly loaded.
Description
30
14
0
0
0
0
29
13
0
0
0
0
Table 12-2. MAC Status Register (MACSR)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 12-3. MACSR Field Descriptions
28
12
0
0
0
0
27
11
0
0
0
Read: 0xE4 (MACSR)
Table continues on the next page...
Write: 0xC4
26
10
0
0
0
PAVn
Preliminary
25
0
0
9
0
24
0
0
8
0
OMC
23
0
0
7
0
S/U
22
0
0
6
0
F/I
21
0
0
5
0
R/T
20
0
0
4
0
Freescale Semiconductor, Inc.
Access: Supervisor read/
19
N
0
0
3
0
BDM read/write
18
Z
0
0
2
0
write
17
V
0
0
1
0
EV
16
0
0
0
0