mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1253

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

For more information on these three BDM command classifications, see
Set
The core's halt mode is entered in a number of ways:
While in halt mode, the core waits for serial background commands rather than executing
instructions from the application program.
Freescale Semiconductor, Inc.
Active background
Command Type
• The BKGD pin is low during POR
• The BKGD pin is low immediately after a BDM-initiated force reset (see
• A background debug force reset occurs (CSR2[BDFR] is set) and CSR2[BFHBR] is
• An illegal operand reset occurs and CSR2[IOPHR] is set
• An illegal address reset occurs and CSR2[IADHR] is set
• A computer operating properly reset occurs and CSR2[ COPHR] is set
• A BACKGROUND command is received through the BKGD pin. If necessary, this
• A properly-enabled (XCSR[ENBDM] is set) HALT instruction is executed
• Encountering a BDM breakpoint and the trigger response is programmed to generate
• Reaching a PSTB trace buffer full condition when operating in an obtrusive
Non-intrusive
Summary.
CSR2[BDFR] in
set
wakes the device from STOP/WAIT modes.
a halt
recording mode (CSR2[PSTBRM] is set to 01 or 11)
Unsecure
Unsecure
Secure?
Flash
Configuration/Status Register 2
Table 50-2. BDM Command Types (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Enabled
Enabled
BDM?
Preliminary
Core Status
Run, Halt
Halt
Command Set
(CSR2), for details)
• Memory access
• Memory access with status
• Debug register access
• BACKGROUND
• Read or write CPU registers (also available
• Single-step the application
• Exit halt mode to return to the application
in stop mode)
program (GO)
BDM Command
Chapter 50 Debug
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