mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 663

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

29.4.6 Calibration function
The ADC contains a self-calibration function that is required to achieve the specified
accuracy. Calibration must be run, or valid calibration values written, after any reset and
before a conversion is initiated. The calibration function sets the offset calibration value
and the plus-side calibration values. The offset calibration value is automatically stored in
the ADC offset correction register (OFS), and the plus-side calibration values are
automatically stored in the ADC plus-side calibration (CLPx) registers. The user must
configure the ADC correctly prior to calibration, and must generate the plus-side gain
calibration results and store them in the ADC plus-side gain register (PG) after the
calibration function completes.
Prior to calibration, the user must configure the ADC's clock source and frequency, low
power configuration, voltage reference selection, sample time, and high speed
configuration according to the application's clock source availability and needs. If the
application uses the ADC in a wide variety of configurations, the configuration for which
the highest accuracy is required should be selected, or multiple calibrations can be done
for the different configurations. For best calibration results, it is recommended to set
hardware averaging to maximum (AVGE=1, AVGS=11 for average of 32), ADC clock
frequency f
voltage and temperature. The input channel, conversion mode continuous function,
compare function, resolution mode, and single-ended mode are all ignored during the
calibration function.
To initiate calibration, the user sets the CAL bit and the calibration will automatically
begin if the ADTRG bit is 0. If ADTRG is 1, the CAL bit will not get set and the
calibration fail flag (CALF) will be set. While calibration is active, no ADC register can
be written and no stop mode may be entered, or the calibration routine will be aborted
causing the CAL bit to clear and the CALF bit to set. At the end of a calibration
sequence, the COCO bit of the SC1A register will be set. The AIEN bit can be used to
allow an interrupt to occur at the end of a calibration sequence. At the end of the
calibration routine, if the CALF bit is not set, the automatic calibration routine completed
successfully.
To complete calibration, the user must generate the gain calibration values using the
following procedure:
Freescale Semiconductor, Inc.
1. Initialize (clear) a 16-bit variable in RAM.
2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, CLPS, and
CLPD to the variable.
ADCK
less than or equal to 4 MHz, V
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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Chapter 29 Analog-to-Digital Converter (ADC)
DDA
, and to calibrate at nominal
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