mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 612

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
27.3.3 RNGB Control Register (RNG_CR)
Through use of this register, the RNGB can be programmed to provide slightly different
functionality based on its desired use.
Address: RNG_CR is FFFF_98C0h base + 8h offset = FFFF_98C8h
612
Reset
Reset
MASKDONE
MASKERR
Bit
Bit
W
W
Reserved
Reserved
R
R
31–10
Field
9–7
6
5
31
15
0
0
30
14
0
0
This read-only bitfield is reserved and always has the value zero.
Reserved, must be cleared.
This read-only bitfield is reserved and always has the value zero.
Reserved, must be cleared.
Mask error interrupt.
Masks interrupts generated by errors in the RNGB. These errors can still be viewed in RNG_ESR.
NOTE: Since masked errors do not interrupt the operation of the RNGB and thus hide potentially fatal
0
1
Mask done interrupt.
Masks interrupts generated upon completion of seed and self test modes. The status of these jobs can be
viewed by:
0
1
• Reading RNG_SR and viewing the seed done and self test done bits (RNG_SR[SDN, STDN])
• Viewing RNG_CMD for generate seed or self test bits (RNG_CMD[GS,ST]) being set, indicating
No mask applied.
Mask applied to the error interrupt.
No mask applied.
Mask applied.
29
13
0
0
that the operation is still taking place.
errors or conditions that could result in corrupted results, it is strongly recommended that errors
only be masked while debugging. All errors are considered fatal, requiring the RNGB to be reset.
Until the a reset occurs, the RNGB does not service any random data.
0
28
12
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
27
11
0
0
RNG_CR field descriptions
Table continues on the next page...
26
10
0
0
25
0
0
9
Preliminary
24
0
0
0
8
0
Description
23
0
0
7
22
0
0
6
21
0
0
5
AR
20
0
0
4
Freescale Semiconductor, Inc.
19
0
0
3
0
18
0
0
2
FUFMOD
17
0
0
1
16
0
0
0