mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 310

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
13.2.16 Clock Gate Control Register 4 (SIM_SCGC4)
Each bit in SCGC4 controls the clock gate to its respective module.
Address: SIM_SCGC4 is FFFF_80C0h base + 15h offset = FFFF_80D5h
310
Reserved
Reserved
WDOG
FTFL
DMA
Reset
Field
IRQ
Read
6–4
Write
7
3
2
1
0
Bit
FTFL
FTFL clock gate control
Controls the clock gate to the FTFL module.
0
1
This bitfield is reserved.
DMA clock gate control
Controls the clock gate to the DMA module.
0
1
This bit is reserved.
IRQ clock gate control
Controls the clock gate to the IRQ module.
0
1
COP clock gate control
Controls the bus clock gate to the COP module.
CAUTION: If the COP is using the bus clock and is enabled and counting, and then the bus clock to the
0
1
7
1
The clock to the module is disabled.
The clock to the module is enabled.
The clock to the module is disabled.
The clock to the module is enabled.
The clock to the module is disabled.
The clock to the module is enabled.
The clock to the module is disabled.
The clock to the module is enabled.
COP is disabled:
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
• The COP cannot be serviced.
• The COP will still time out and cause a reset.
SIM_SCGC4 field descriptions
Reserved
0
5
Preliminary
0
4
Description
DMA
0
3
Reserved
0
2
Freescale Semiconductor, Inc.
IRQ
0
1
WDOG
1
0