mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 826

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Definition
826
DECAPEN
COMBINE
DECAP
COMP
DTEN
Field
4
3
2
1
0
Deadtime Enable
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
1
Dual Edge Capture Mode Captures
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when MODE[FTMEN] = 1 and DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0
1
Dual Edge Capture Mode Enable
Enables the dual edge capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in dual edge capture mode according to the table
Mode, Edge, and Level Selection in the description of the CnSC register.
This field applies only when MODE[FTMEN] = 1.
DECAPEN is write protected, this bit can only be written if MODE[WPDIS] = 1.
0
1
Complement of Channel (n)
Enables complementary mode for the combined channels. In complementary mode the channel (n+1)
output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
1
Combine Channels
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0
1
The deadtime insertion in this pair of channels is disabled.
The deadtime insertion in this pair of channels is enabled.
The dual edge captures are inactive.
The dual edge captures are active.
The dual edge capture mode in this pair of channels is disabled.
The dual edge capture mode in this pair of channels is enabled.
The channel (n+1) output is the same as the channel (n) output.
The channel (n+1) output is the complement of the channel (n) output.
Channels (n) and (n+1) are independent.
Channels (n) and (n+1) are combined.
FTMx_COMBINEn field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Description
Freescale Semiconductor, Inc.