mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 348

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
15.4.6 Set Interrupt Mask Register (INTC_SIMR)
The INTC_SIMR register provides a simple memory-mapped mechanism to set a given
bit in the INTC_IMR{H,L} registers to disable (mask) a given interrupt request. The data
value on a register write causes the corresponding bit in the INTC_IMR{H,L} registers to
be set. Setting INTC_SIMR[SALL] forces the entire contents of INTC_IMR{H,L}
registers to set, masking all interrupts. Attempting to read this register generates an error
termination.
IMR[63:44] are reserved for future use, so writes using these data values are ignored.
This register is provided so interrupt service routines can easily mask the given interrupt
request without the need to perform a read-modify-write sequence on the
INTC_IMR{H,L} registers.
Address: INTC_SIMR is FFFF_FFC0h base + 1Ch offset = FFFF_FFDCh
348
Reserved
Reserved
MASK
SALL
SIMR
Field
Reset
Field
6–3
2–0
Read
5–0
Write
7
6
Bit
Reserved
This read-only bitfield is reserved and always has the value zero.
Interrupt mask level
This bit is reserved.
Set all
Set all bits in the INTC_IMR{H,L} register, masking all interrupt requests.
0
1
Set IMR
Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request.
7
0
Set only those bits specified in the SIMR field.
Set all bits in INTC_IMR{H,L} register. The SIMR field is ignored.
SALL
INTC_WCR field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
INTC_SIMR field descriptions
0
5
Preliminary
0
4
Description
Description
0
3
SIMR
0
2
Freescale Semiconductor, Inc.
0
1
0
0