mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 892

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
is set when the second rising edge is detected, that is, the edge selected by ELS(n
+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the period were
captured and the C(n)VH:L and C(n+1)VH:L registers are ready for reading.
37.4.22.5 Read Coherency Mechanism
The dual edge capture mode implements a read coherency mechanism between the FTM
counter value captured in C(n)VH:L and C(n+1)VH:L registers. The read coherency
mechanism is illustrated in the following figure. In this example, the channels (n) and (n
+1) are in dual edge capture – continuous mode for positive polarity pulse width
measurement. Thus, the channel (n) is configured to capture the FTM counter value when
there is a rising edge at channel (n) input signal, and channel (n+1) to capture the FTM
counter value when there is a falling edge at channel (n) input signal.
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Figure 37-214. Dual Edge Capture – Continuous Mode to Measure of the Period Between
Note:
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
channel (n) input
DECAPEN bit
(after the filter
channel input)
CH(n+1)F bit
C(n+1)VH:L
DECAP bit
FTM counter
CH(n)F bit
C(n)VH:L
clear CH(n+1)F
clear CH(n)F
set DECAPEN
set DECAP
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MCF51JF128 Reference Manual, Rev. 2, 03/2011
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