mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1254

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

External Signal Descriptions
The preceding figure contains a simplified view of the V1 ColdFire debug mode states.
The XCSR[CLKSW] bit controls the BDC clock source. When CLKSW is set, the BDC
serial clock frequency is half the CPU clock. When CLKSW is cleared, the BDC serial
clock is supplied from an alternate clock source .
The ENBDM bit determines if the device can be placed in halt mode, if the core and
BDC serial clocks continue to run in STOP modes, and if the regulator can be placed into
standby mode. Again, if booting to halt mode, XCSR[ENBDM, CLKSW] are
automatically set.
If ENBDM is cleared, the ColdFire core treats the HALT instruction as an illegal
instruction and generates a reset (if CPUCR[IRD] is cleared) or an exception (if
CPUCR[IRD] is set) if execution is attempted.
If XCSR[ENBDM] is set, the device can be restarted from STOP/WAIT via the BDM
interface.
50.2 External Signal Descriptions
The following table describes the debug module's 1-pin external signal (BKGD). A
standard 6-pin debug connector is shown in
1254
Illegal address reset and CSR2[IADHR]=1
Illegal op reset and CSR2[IOPHR]=1 or
COP reset and CSR2[COPHR]=1 or
(POR or BDFR=1) with BKGD=0 or
BDFR, BFHBR, and BKGD=1 or
BDFR=1 and BFHBR=0 or
POR with BKGD=1 or
BDFR and BFHBR= 1 or
any other reset
Figure 50-2. Debug Modes State Transition Diagram
CPU clock/2 is used
as the BDM clock
MCF51JF128 Reference Manual, Rev. 2, 03/2011
BDM & CPU clocks are not
enabled in STOP modes
State
Any
Debug not enabled
CLKSW=1
CLKSW=0
Preliminary
ENBDM=1
ENBDM=0
Operation
Normal
Debug
Freescale-Recommended BDM
Halt
clear ENBDM
command
BDM GO
via BDM
BACKGROUND command,
ENBDM
ENBDM=1
Operation
Normal
HALT instruction, or
Set
Return to Halt via
BDM breakpoint trigger
Freescale Semiconductor, Inc.
CPU clocks continue
during STOP modes
Debug is enabled
Pinout.