mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 743

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

33.4.4 Pulse-Out's
PDB can generate pulse outputs of configurable width. When PDB counter reaches the
value set in POyDLY[DLY1], the Pulse-Out goes high; when the counter reaches
POyDLY[DLY2], it goes low. POyDLY[DLY2] can be set either greater or less than
POyDLY[DLY1].
Because the PDB counter is shared by both ADC pre-trigger/trigger outputs and Pulse-
Out generation, they have the same time base.
The pulse-out connections implemented in this MCU are described in the device's Chip
Configuration details.
33.4.5 Updating the Delay Registers
The following registers control the timing of the PDB operation; and in some of the
applications, they may need to become effective at the same time.
Freescale Semiconductor, Inc.
PDB
counter
Trigger input event
DAC internal trigger x
Ch n pre-trigger 0
Ch n pre-trigger 1
PDB interrupt
Ch n trigger
Figure 33-43. PDB ADC Triggers and DAC Interval Triggers Use Case
DACINTx x3
DACINTx x2
DACINTx
0
Because the DAC interval counters share the prescaler with
PDB counter, PDB must be enabled if the DAC interval trigger
outputs are used in the applications.
CHnDLY1
CHnDLY0
MOD, IDLY
MCF51JF128 Reference Manual, Rev. 2, 03/2011
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Preliminary
NOTE
Chapter 33 Programmable Delay Block (PDB)
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