mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 259

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Information loaded into D1 defines the local memory hardware configuration as shown in
the figure below.
Freescale Semiconductor, Inc.
Table 11-20. D0 Hardware Configuration Information Field Descriptions (continued)
Reset
BDM:
DEBUG
EMAC
19–16
Field
REV
CAU
W
W
DIV
9–8
7–4
3–0
R
R
ISA
15
14
13
12
11
10
31
15
FLASHSZ
30
14
DEPART
Table 11-21. D1 Hardware Configuration Information
Processor revision number
Reserved
Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.
0
1
EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution
engine is present in processor core.
0
1
Reserved
Reserved
Cryptographic acceleration unit present. This bit signals if the optional cryptographic acceleration
unit (CAU) is present in the processor core.
0
1
Reserved
ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire
processor core.
0010
Debug module revision number. Defines revision level of the debug module used in the ColdFire
processor core.
1001
Description
29
13
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
12
Divide execute engine not present in core
Divide execute engine is present in core
EMAC execute engine not present in core
EMAC execute engine is present in core
CAU coprocessor engine not present in core
CAU coprocessor engine is present in core
ISA_C
DEBUG_B+
27
11
FLASHH
Table continues on the next page...
Store: 0x41 (D1)
Load: 0x61 (D1)
26
10
Preliminary
25
Reserved
9
Device-specific
FLEXNVMSZ
24
8
23
7
22
6
FLEXNVMH
21
5
RAMSZ
20
4
19
Access: User read-only
3
BDM read-only
RAM
18
EEESIZE
H
2
Chapter 11 Core
17
1
16
0
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