mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 405

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

18.4 I/O Retention
When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the
power management control (PMC) is re-enabled, goes through a power up sequence to
full regulation, and releases the logic from state retention mode. The I/O are released
immediately after ACKISO clears, soon after a wakeup or reset event. In the case of LLS
exit via a RESET pin, the I/O default to their reset state.
When in VLLS modes, the I/O states are held on a wakeup event (with the exception of
wakeup by reset event) until the wakeup has been acknowledged via a write to the
ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default
to their reset state. In this case, no write to the ACKISO is needed.
18.5 Memory Map and Register Descriptions
PMC register details follow.
Freescale Semiconductor, Inc.
FFFF_8100
FFFF_8101
FFFF_8102
Absolute
address
(hex)
Low Voltage Detect Status and Control 1 Register
(PMC_LVDSC1)
Low Voltage Detect Status and Control 2 Register
(PMC_LVDSC2)
Regulator Status and Control Register (PMC_REGSC)
Different portions of PMC registers are reset only by particular
reset types. Each register's description provides details. For
more information about the types of reset on this chip, refer to
the
Reset
details.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Register name
PMC memory map
Preliminary
NOTE
Chapter 18 Power Management Controller (PMC)
(in bits)
Width
8
8
8
Access
R/W
R/W
R/W
Reset value
10h
00h
04h
18.5.1/406
18.5.2/407
18.5.3/408
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