mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 884

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Functional Description
The initialization trigger output provides a trigger signal that is used for on-chip modules.
37.4.20 Capture Test Mode
The capture test mode allows the testing of the CnVH:L registers, the FTM counter and
the interconnection logic between the FTM counter and CnVH:L registers.
In this test mode, all channels must be configured for input capture mode (see
Capture
When the capture test mode is enabled (CAPTEST = 1), the FTM counter is frozen and
any write to CNTH and CNTL updates directly the FTM counter (see the following
figure). After both bytes were written (independent of the order), all CnVH:L registers
are updated with the value that was written to CNTH:L registers and CHnF bits are set.
Therefore, the FTM counter is updated with its next value according to its configuration
(its next value depends on CNTINH:L, MODH:L, and the value that was written to FTM
counter).
The next reads of CnVH:L registers return the value that was written to FTM counter and
the next reads of CNTH:L register return the next value of the FTM counter.
The read coherency mechanism of CNTH:L and CnVH:L registers remains enabled.
884
Mode) and FTM counter must be configured for up-counting (see
Initialization trigger is only available in combine mode.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Note
Freescale Semiconductor, Inc.
Up
Input
Counting).

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