mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 243

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

11.2.8 Status register (SR)
This register stores the processor status and includes the CCR, the interrupt priority mask,
and other control bits. In supervisor mode, software can access the entire SR. In user
mode, only the lower 8 bits (the CCR) are accessible. The control bits indicate the
following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and
master or interrupt state (M bit). All defined bits in the SR have read/write access when
in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after
reset and before any compare (CMP), Bcc, or Scc instructions execute.
Freescale Semiconductor, Inc.
Reset
BDM:
FDCEN
FICDIS
FCCLR
FCDIS
18–0
Field
W
R
22
21
20
19
15
T
0
14
0
0
Flash controller cache disable
Disables the caching of the flash read data. This bit overrides the instruction and data cache
enables.
0
1
Flash data caching enable
Enables the caching of operand fetches from the flash memory controller.
0
1
Flash instruction caching disable
Disables the caching of instruction fetches from the flash memory controller.
0
1
Clear flash controller cache
Setting this bit to 1 clears (invalidates) the cache immediately. This bit always reads as 0.
Reserved; must be cleared.
Description
Table 11-10. CPUCR field descriptions (continued)
13
S
1
MCF51JF128 Reference Manual, Rev. 2, 03/2011
12
M
0
The flash controller's cache is enabled. Use the instruction and data cache enable bits
to decide which accesses are cached.
The flash controller's cache is disabled. (lower performance)
Data accesses via the flash controller cache are disabled.
Data accesses via the flash controller cache are enabled.
Instruction fetches via the flash controller cache are enabled.
Instruction fetches via the flash controller cache are disabled.
Table 11-11. Status register (SR)
11
0
0
Store: 0xCE (SR)
Load: 0xEE (SR)
10
1
Preliminary
9
1
I
8
1
0
7
0
6
0
0
5
0
0
4
X
–
Access: Supervisor read/
N
3
–
BDM read/write
Z
2
–
Chapter 11 Core
write
V
1
–
C
0
–
243