mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1332

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Clock Distribution chapter changes
A.5 Clock Distribution chapter changes
A.6 Reset and Boot chapter changes
A.7 Power Management chapter changes
A.8 Security chapter changes
A.9 Signal Multiplexing and Signal Descriptions chapter
A.10 MXC changes
1332
In "Stop mode acknowledge error (SACKERR)" section, updated the number of 1 kHz LPO clock cycles.
Corrected and expanded the Multipurpose Clock Generator loss of clock (LOC) section.
In "Module operation in low power modes" table:
• From main clocking diagram, removed MCGFLLCLK routing to SAICLK
• In Device Clock Summary table, corrected MCGFFCLK information for run mode and VLPR mode
• In USB 48 MHz Clock Source diagram, corrected SIM register reference
• Added RCM to group of System modules.
• Corrected information about MCG in VLPS mode.
• No substantial content changes
• For PTB4, clarified that ALT2 setting is BKGD/MS and ALT3 setting is not applicable.
• For PTB0, clarified that default and ALT5 setting is IRQ/EZP_MS_b.
• Corrected reset values of PTBPF2, PTBPF4, and PTCPF4 registers.
• In the description of the PTBPF2[B4] field, clarified that setting value 0010 is for BKGD/MS and that setting value 0011
• In the description of the PTBPF4[B0] field, clarified that setting value 0101 is for IRQ/EZP_MS_b.
is reserved.
changes
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.

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