mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 933

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 38 Serial Peripheral Interface (SPI)
38.4.7 SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different
manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA)
control bit to select one of four clock formats for data transfers. CPOL selectively inserts
an inverter in series with the clock. CPHA chooses between two different clock phase
relationships between the clock and data.
The following figure shows the clock formats when SPIMODE = 0 (8-bit mode) and
CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1
starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the eighth
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits
depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but
only one of these waveforms applies for a specific transfer, depending on the value in
CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO
input of a master. The MOSI waveform applies to the MOSI output pin from a master
and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided MODFEN and
SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the
start of the transfer and goes back high at the end of the eighth bit time of the transfer.
The SS IN waveform applies to the slave select input of a slave.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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