mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1072

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Memory Map
1072
RWUID
LBKDE
BRK13
RXINV
Field
RAF
4
3
2
1
0
is automatically set or cleared when C7816[INIT] and C7816[ISO7816E] are enabled and an initial
character is detected.
0
1
Receive Data Inversion
Setting this bit, reverses the polarity of the received data input. In NRZ format, a one is represented by a
mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. This
bit is automatically set or cleared when C7816[INIT] and C7816[ISO7816E] are enabled and an initial
character is detected.
NOTE: Setting RXINV inverts the RxD input for: data bits, start and stop bits, break, and idle. When
0
1
Receive Wakeup Idle Detect
When RWU is set and WAKE is cleared, this bit controls whether the idle character that wakes the
receiver sets the S1[IDLE] bit.This bit must be cleared when C7816[ISO7816E] is set/enabled.
0
1
Break Transmit Character Length
This bit determines whether the transmit break character is 10, 11, or 12 bits long, or 13 or 14 bits long.
Refer to
configurations. The detection of a framing error is not affected by this bit.
0
1
LIN Break Detection Enable
LBKDE selects a longer break character detection length. While LBKDE is set, the S1[RDRF], S1[NF],
S1[FE], and S1[PF] flags are prevented from setting. When LBKDE is set, see
LBKDE bit must be cleared when C7816[ISO7816E] is set.
0
1
Receiver Active Flag
RAF is set when the UART receiver detects a logic 0 during the RT1 time period of the start bit search.
RAF is cleared when the receiver detects an idle character when C7816[ISO7816E] is cleared/disabled.
When C7816[ISO7816E] is enabled the RAF is cleared if the C7816[TTYPE] = 0 expires or the
C7816[TTYPE] = 1 expires.
NOTE: In the case when C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible to configure the
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the
start bit is identified as bit0.
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting
of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7 or bit6
depending on the setting of C1[M] and C1[PE].
Receive data is not inverted.
Receive data is inverted.
The S1[IDLE] bit is not set upon detection of an idle character.
The S1[IDLE] bit is set upon detection of an idle character.
Break character is 10, 11, or 12 bits long.
Break character is 13 or 14 bits long.
Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or
12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).
Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).
Transmitting break characters
C7816[ISO7816E] is set/enabled then only the data bits and the parity bit are inverted.
guard time to be 12. However, in the event that a NACK is required to be transmitted the data
UARTx_S2 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table continues on the next page...
Preliminary
for the length of the break character for the different
Description
Freescale Semiconductor, Inc.
Overrun
operation. The