mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 786

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The carrier signal is generated by counting a register-selected number of input clocks
(125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The
period is determined by the total number of clocks counted. The duty cycle is determined
by the ratio of high time clocks to total clocks counted. The high and low time values are
user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the
generation of dual frequency FSK (frequency shift keying) protocols without CPU
intervention.
MSC[MCGEN] bit must be set and MSC[BASE] bit must be cleared to enable carrier
generator clocks. When MSC[BASE] bit is set, the carrier output to the modulator is held
high continuously. Following figure represents the block diagram of the clock generator.
The high/low time counter is an 8-bit up counter. After each increment, the contents of
the counter are compared with the appropriate high or low count value register. When the
compare value is reached, the counter is reset to a value of 0x01, and the compare is
redirected to the other count value register.
786
CARRIER OUT (f cg )
Only non-zero data values are allowed. The carrier generator
will not work if any of the count values are equal to zero.
MCGEN
CMTCLK
BASE
FSK
Figure 36-15. Carrier Generator Block Diagram
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SECONDARY HIGH COUNT REGISTER
SECONDARY LOW COUNT REGISTER
PRIMARY HIGH COUNT REGISTER
PRIMARY LOW COUNT REGISTER
CLK
CLR
8-BIT UP COUNTER
Preliminary
= ?
= ?
Note
Freescale Semiconductor, Inc.
PRIMARY/
SECONDARY
SELECT