mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 430

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates
transfer size. For example, AA equals 1, SARn equals 0x(00)80_0001, BCRn equals
0x00_00F0, SSIZE equals 00 (longword), and DSIZE equals 01 (byte). Because SSIZE >
DSIZE, the source is auto-aligned. Error checking is performed on destination registers.
The access sequence is as follows:
If DSIZE is another size, data writes are optimized to write the largest size allowed based
on the address, but not exceeding the configured size.
19.4.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
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1. Read byte from 0x(00)80_0001, increment SARn, write 1 byte (using DARn).
2. Read word from 0x(00)80_0002, increment SARn, write 2 bytes.
3. Read longword from 0x(00)80_0004, increment SARn, write 4 bytes.
4. Repeat longwords until SARn = 0x(00)80_00F0.
5. Read byte from 0x(00)80_00F0, increment SARn, write byte.
• Error conditions—When the DMA encounters a read or write cycle that terminates
• Interrupts—If DCRn[EINT] is set, the DMA drives the appropriate interrupt request
with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a
write before the transfer is halted. If the error occurred in a write cycle, data in the
internal holding registers is lost.
signal. The processor can read DSRn to determine whether the transfer terminated
successfully or with an error. DSRn[DONE] is then written with a one to clear the
interrupt, the DONE, and error status bits.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.