mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 924

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
38.4 Functional Description
This section provides the functional description of the module.
38.4.1 General
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1.
While the SPE bit is set, the four associated SPI port pins are dedicated to the SPI
function as:
924
TNEAREFCI
RNFULLFCI
• Slave select (SS)
• Serial clock (SPSCK)
SPTEFCI
RXFERR
SPRFCI
RXFOF
TXFOF
Field
6
5
4
3
2
1
0
Receive FIFO error flag
This flag indicates that a receive FIFO error occurred because entries in the FIFO exceed 8.
0
1
Transmit FIFO overflow flag
This flag indicates that a transmit FIFO overflow condition has occurred.
0
1
Receive FIFO overflow flag
This flag indicates that a receive FIFO overflow condition has occurred.
0
1
Transmit FIFO nearly empty flag clear interrupt
Writing 1 to this bit clears the TNEAREF interrupt provided that C3[3] is set.
Receive FIFO nearly full flag clear interrupt
Writing 1 to this bit clears the RNFULLF interrupt provided that C3[3] is set.
Transmit FIFO empty flag clear interrupt
Writing 1 to this bit clears the SPTEF interrupt provided that C3[3] is set.
Receive FIFO full flag clear interrupt
Writing 1 to this bit clears the SPRF interrupt provided that C3[3] is set.
No receive FIFO error occurred
A receive FIFO error occurred
Transmit FIFO overflow condition has not occurred
Transmit FIFO overflow condition occurred
Receive FIFO overflow condition has not occurred
Receive FIFO overflow condition occurred
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_CI field descriptions (continued)
Preliminary
Description
Freescale Semiconductor, Inc.