mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 726

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Introduction
33.1.2 Implementation
In this chapter, the following letters refers to the number of output triggers.
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• Up to eight DAC interval triggers
• Up to eight pulse outputs (pulse-out's)
• N — Total available number of PDB channels.
• n — PDB channel number, valid from 0 to N-1.
• M — Total available pre-trigger per PDB channel.
• m — Pre-trigger number, valid from 0 to M-1.
• X — Total number of DAC interval triggers.
• x — DAC interval trigger output number, valid from 0 to X-1.
• Y — Total number of Pulse-Out's.
• y — Pulse-Out number, valid value is 0 to Y-1.
• One channel flag and one sequence error flag per pre-trigger
• DMA support
• One interval trigger output per DAC
• One 16-bit delay interval register per DAC trigger output
• Optional bypass the delay interval trigger registers
• Optional external triggers
• Pulse-out's can be enabled or disabled independently.
• Programmable pulse width
The number of PDB input and output triggers are chip-specific.
Refer to the Chip Configuration information for details.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
NOTE
Freescale Semiconductor, Inc.