mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 396

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The V1 ColdFire core does not differentiate between STOP and WAIT modes. Both are
considered STOP mode from the core’s perspective. The difference between the two is at
the device level. In STOP mode, most peripheral clocks are shut down. In WAIT mode,
the global peripheral clocks continue to run and can be enabled or disabled on a per
peripheral basis using clock gating control bits in the SIM.
When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in
RUN mode, beginning with the stacking operations leading to the interrupt service
routine.
A system reset will cause an exit from WAIT mode, returning the device to normal RUN
mode.
17.4.4.2 Very Low Power Wait (VLPW) Mode
VLPW mode is entered by executing a STOP instruction while the MCU is in very low
power run (VLPR) mode and configured as per
Table
17-7.
In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state,
the regulator is designed to supply enough current to the MCU over a reduced frequency.
To further reduce power in this mode, disable the clocks to unused modules by clearing
the peripherals' corresponding clock gating control bits in the SIM.
VLPR mode restrictions also apply to VLPW.
VLPW mode provides the option to return to full-regulated normal RUN mode if any
enabled interrupt occurs. This is done by setting the low power wake up on interrupt
(LPWUI) bit in the PMCTRL register. Wait for the PMSTAT register to set to RUN
before increasing the frequency.
If the LPWUI bit is clear, when an interrupt from VLPW occurs, the device returns to
VLPR mode to execute the interrupt service routine.
A system reset will cause an exit from WAIT mode, returning the device to normal RUN
mode.
17.4.4.3 BDM in Wait and VLPW Mode
If the MCU is unsecure, BDM mode is enabled, and XCSR[ENBDM] is set prior to
entering wait then the MCU can support debugging using the BDM.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
396
Freescale Semiconductor, Inc.