mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1153

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
44.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)
Addresses: I2S0_RCR1 is FFFF_8200h base + 84h offset = FFFF_8284h
44.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)
This register cannot be altered when the receive enable bit is set.
Addresses: I2S0_RCR2 is FFFF_8200h base + 88h offset = FFFF_8288h
Freescale Semiconductor, Inc.
Reset
Reset
Bit
W
R
Bit
Bit
Reserved
W
W
31
0
R
R
RFW
31–2
Field
Field
1–0
30
0
31
15
0
0
29
0
28
0
30
14
0
0
0
1
This read-only bitfield is reserved and always has the value zero.
Receive FIFO watermark
Configures the watermark level for all enabled receiver channels.
27
0
0
Disables the DMA request.
Enables the DMA request.
26
0
29
13
0
0
25
0
24
0
28
12
0
0
I2Sx_RCSR field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
0
CLKMODE
22
0
27
11
0
0
Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_RCR1 field descriptions
21
0
20
0
26
10
0
0
19
0
BCP
18
25
0
0
0
9
Preliminary
17
0
0
BCD
16
24
0
0
0
8
15
0
Description
Description
23
14
0
0
7
0
13
0
22
0
0
12
6
0
11
0
21
0
0
5
10
0
0
9
20
0
0
4
0
8
DIV
0
0
7
19
0
0
3
0
6
0
5
18
0
0
2
4
0
0
3
17
0
0
1
0
2
0
1
1153
16
0
0
0
0
0