mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 533

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

23.4.11.9 Read 1s All Blocks Command
The Read 1s All Blocks command checks if the program flash blocks, data flash blocks,
FlexRAM, EEPROM backup records, and data flash IFR have been erased to the
specified read margin level, if applicable, and releases security if the readout passes, i.e.
all data reads as '1'.
After clearing CCIF to launch the Read 1s All Blocks command, the FTFL :
If the FTFL confirms that these memory resources are erased, security is released by
setting the FSEC[SEC] field to the unsecure state. The security byte in the flash
configuration field (see
Read 1s All Blocks command. If the read fails, i.e. all memory resources are not in the
fully erased state, the FSTAT[MGSTAT0] bit is set.
The EEERDY and RAMRDY bits are clear during the Read 1s All Blocks operation and
are restored at the end of the Read 1s All Blocks operation.
The CCIF flag sets after the Read 1s All Blocks operation has completed.
Freescale Semiconductor, Inc.
An invalid margin choice is specified
Read-1s fails
Error Condition
Read Margin Choice
• sets the read margin for 1s according to
• checks the contents of the program flash, data flash, EEPROM backup records, data
FCCOB Number
flash IFR, and FlexRAM are in the erased state.
0x00
0x01
0x02
0
1
Table 23-53. Read 1s All Blocks Command FCCOB Requirements
Table 23-55. Read 1s All Blocks Command Error Handling
Table 23-54. Margin Level Choices for Read 1s All Blocks
Flash Configuration Field
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Apply the 'Factory' margin to the normal read-1 level
Apply the 'User' margin to the normal read-1 level
Preliminary
Use the 'normal' read level for 1s
Table
Margin Level Description
FCCOB Contents [7:0]
Read-1 Margin Choice
0x40 (RD1ALL)
Description) remains unaffected by the
23-54,
Chapter 23 Flash Memory Module (FTFL)
FSTAT[MGSTAT0]
FSTAT[ACCERR]
Error Bit
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