HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 98
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place
oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal
lines cross this line. Separate PLLVcL and PLLVss circuit against Vcc and Vss circuit from the
board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins.
Electromagnetic waves are radiated from an LSI in operation. This LSI has an electromagnetic
peak in the harmonics band whose primary frequency is determined by the lower frequency
between the system clock (φ) and peripheral clock (Pφ). For example, when φ = 50 MHz and Pφ =
40 MHz, the primary frequency is 40 MHz. If this LSI is used adjacent to a device sensitive to
electromagnetic interference, e.g. FM/VHF band receiver, a printed circuit board of more than
four layers with planes exclusively for system ground is recommended.
Rev. 2.00, 09/04, page 56 of 720
Note: * CB and CPB are laminated ceramic type.
Figure 4.6 Recommended External Circuitry Around the PLL
PLLCAP
PLLV
PLLV
V
V
CC
CL
SS
SS
R1: 3kΩ
CPB = 0.47 µF *
CB = 0.47 µF *
C1: 470 pF
(Values are recommended values.)
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