HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 537

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Initial Settings: In the operating modes, there are five registers that require initialization.
Make the following register settings before setting the operating mode with bits MD1 and MD0 in
the timer mode register (TMDR).
Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the
timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set
{TPBR value + 2Td} in the timer period data register (TPDR).
Set {PWM duty initial value – Td} in the free write operation addresses for TBRU to TBRW.
The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the
value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td.
(1/2 period)
TDCNT
(TBR)
TDDR
TBRU
TBRV
TBRW
TPBR
TDDR
TDDR
(Td)
(Td)
(Td)
×2
×2
Figure 16.4 Examples of Counter and Register Operations
+
+
Up-count → compare match → halt
+
(1/2 period + 2Td)
TGRUU
TGRVU
TGRWU
TGRU
TGRV
TGRW
TGRUD
TGRVD
TGRWD
(2Td)
TCNT
TPDR
(TBR + 2Td)
(TBR + Td)
(TBR)
TCNT
Compared during
up-count
Compared during
down-count
Rev. 2.00, 09/04, page 495 of 720
Up-count → compare
match → down-count
Down-count → compare
match → up-count
Compared during
up-count
Constantly
compared
Compared during
down-count

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