HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 756

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 714 of 720
Item
Section 20 Mask ROM
Figure 24.1 Mode
Transition Diagram
24.3.2 Software Standby
Mode
Table 25.2 DC
Characteristics
Table 25.6 Bus Timing
Page
577
605
611
620
629
Revisions (See Manual for Details)
If you are using the on-chip ROM, select mode 2 or mode 3; if
you are not, select mode 0 or mode 1. The on-chip ROM is
allocated to addresses H'00000000 to H'0001FFFF.
Notes: * NMI and IRQ
Transition to Software Standby Mode:
However, the contents of the CPU's internal registers and on-
chip RAM data are retained as long as the specified voltage is
supplied.
Notes: 1. See page 2 for correspondence of the standard product, wide
Item
Schmitt trigger
input voltage
Item
CS delay time 1
CS delay time 2
WAIT setup time
WAIT hold time
Read data access time
Access time from read strobe
Write address setup time
Write address hold time
Write data hold time
2. n is the number of wait cycles.
3. At the CS assert period extension, t
4. At the CS assert period extension, t
5. At the CS assert period extension, 5 + t
temperature-range product, and product model name.
IRQ3 to IRQ0,
POE6 to POE0, TCLKA to TCLKD,
TIOC0A to TIOC0D, TIOC1A, TIOC1B,
TIOC2A, TIOC2B, TIOC3A to TIOC3D,
TIOC4A to TIOC4D
:
Symbol
t
t
t
t
t
t
t
t
t
CSD1
CSD2
WTS
WTH
ACC
OE
AS
WR
WRH
CYC
CYC
.
× (3 + n) - 35.
CYC
.
Symbol
V
V
V
T+
T–
T+
Min
—
—
15
0
t
(2+n)-35*
t
(1.5+n)-33*
0*
5*
0*
CYC
CYC
–V
(V
(V
4
5
4
×
×
T–
IH
IL
)
)
2
*
3
2