HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 466

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 424 of 720
Bit
9
8
Bit Name
IRR9
IRR8
Initial
Value
0
0
R/W
R
R/W
Description
Unread Message Interrupt Flag
Status flag indicating that a message has been received
but the existing message in that mailbox has not yet been
read due to the corresponding RXPR or RFPR set to 1.
The received message is either ignored (overrun) or
overwritten depending on the NMC (new message
control) bit.
Note: To clear this bit, clear the UMSR bit by writing 1 to
0: No message overrun or overwritten
1: Receive message overrun or overwritten
[Clearing condition]
•
[Setting conditions]
•
•
Mailbox Empty Interrupt Flag
This bit is set when at least one TXPR bit is cleared. It is
a status flag indicating that the mailbox is now ready to
accept a new transmit message. In effect, this bit is set
when any bit in TXACK or ABACK is set, therefore, this
bit is automatically cleared when all the TXACK and
ABACK bits are cleared.
0: Transmission or transmission abort of a message is not
1: Message has been transmitted or aborted, and new
[Clearing condition]
•
[Setting condition]
•
Note: This bit does not indicate that all TXPR bits are
yet carried out.
message can be stored
All the UMSR bits are cleared
Message is received while the corresponding RXPR
or RFPR = 1 and MBIMR = 0
Any UMSR bit is set
When all the TXACK and ABACK bits are cleared
When one of the TXPR (transmit wait) bits is cleared
by completion of transmission or completion of
transmission abort, i.e., when a TXACK or ABACK bit
is set (if MBIMR = 0).
corresponding UMSR bit. Writing 0 has no effect.
reset.