HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 267

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Example of Complementary PWM Mode Setting Procedure: An example of the
complementary PWM mode setting procedure is shown in Figure 10.33.
1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter
2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2–TPSC0 and
3. When performing brushless DC motor control, set bit BDC in the timer gate control register
4. Set the dead time in TCNT_3. Set TCNT_4 to H'0000.
5. Set only when restarting by a synchronous clear from another channel during complementary
6. Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer
7. Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle
8. Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE
9. Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A,
10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable
11. Set the port control and port I/O registers.
12. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation.
(TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4
are stopped.
bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2–CCLR0 to set
synchronous clearing only when restarting by a synchronous clear from another channel during
complementary PWM mode operation.
(TGCR) and set the feedback signal input source and output chopping or gate signal direct
output.
PWM mode operation. In this case, synchronize the channel generating the synchronous clear
with channels 3 and 4 using the timer synchro register (TSYR).
registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding
TGR.
data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus
the dead time in TGRA_3 and TGRC_3.
in the timer output control register (TOCR), and set the PWM output level with bits OLSP and
OLSN.
TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins*. Do
not set in TMDR_4.
register (TOER).
Rev. 2.00, 09/04, page 225 of 720