HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 407

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.2
Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
12.12 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDRF
RDR
value
MPIE
RDRF
RDR
value
Figure 12.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Serial Data Reception
1
1
Start
bit
Start
bit
0
0
MPIE = 0
MPIE = 0
D0
D0
ID1
D1
D1
Data (ID1)
Data (ID2)
RXI interrupt
request
(multiprocessor
interrupt)
generated
RXI interrupt
request
(multiprocessor
interrupt)
generated
Multiprocessor Bit, One Stop Bit)
D7
D7
(a) Data does not match station’s ID
(b) Data matches station’s ID
MPB
MPB
1
1
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
Stop
bit
Stop
bit
1
1
Start
bit
Start
bit
0
0
D0
D0
If not this station’s ID,
MPIE bit is set to 1
again
Matches this station’s ID,
so reception continues,
and data is received in RXI
interrupt processing routine
D1
D1
Data (Data1)
Data (Data2)
Rev. 2.00, 09/04, page 365 of 720
ID2
ID1
D7
D7
MPB
MPB
0
0
RXI interrupt request is
not generated, and RDR
retains its state
Stop
bit
Stop
bit
1
1
MPIE bit is set to 1
again
Idle state
(mark state)
Idle state
(mark state)
Data2
1
1