HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 379

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Bit
7
6
Bit Name
TDRE
RDRF
Serial Status Register (SSR)
Initial
Value
1
0
R/W
R/(W)*
R/(W)*
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
•
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared to
0.
Power-on reset, hardware standby mode, or
software standby mode
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
data can be written to TDR
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt
request and transferred data to TDR
When serial reception ends normally and receive
data is transferred from RSR to RDR
Power-on reset, hardware standby mode, or
software standby mode
When 0 is written to RDRF after reading RDRF = 1
When the DTC is activated by an RXI interrupt and
transferred data from RDR
Rev. 2.00, 09/04, page 337 of 720