HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 300

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.7
10.7.1
MTU operation can be disabled or enabled using the module standby register. The initial setting is
for MTU operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 24, Power-Down Modes.
10.7.2
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.43 shows the input clock
conditions in phase counting mode.
Rev. 2.00, 09/04, page 258 of 720
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes: Phase difference and overlap
Figure 10.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Pulse width
Usage Notes
Module Standby Mode Setting
Input Clock Restrictions
Overlap
Pulse width
Phase
differ-
ence
Overlap
: 1.5 states or more
: 2.5 states or more
Phase
differ-
ence
Pulse width
Pulse width
Pulse width