HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 224

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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10.3.5
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU has five TSR registers, one for each channel.
Rev. 2.00, 09/04, page 182 of 720
Bit
7
6
5
4
Bit Name
TCFD
TCFU
TCFV
Timer Status Register (TSR)
Initial
value
1
1
0
0
R
R/(W)
R/W
R
R/(W)
Description
Count Direction Flag
Status flag that shows the direction in which TCNT counts in
channels 1, 2, 3, and 4.
In channel 0, bit 7 is reserved. It is always read as 1, and
should only be written with 1.
0: TCNT counts down
1: TCNT counts up
Reserved
This bit is always read as 1, and should only be written with
1.
Underflow Flag
Status flag that indicates that TCNT underflow has occurred
when channels 1 and 2 are set to phase counting mode.
Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always read
as 0, and should only be written with 0.
[Setting condition]
[Clearing condition]
Overflow Flag
Status flag that indicates that TCNT overflow has occurred.
Only 0 can be written, for flag clearing.
[Setting condition]
[Clearing condition]
When the TCNT value underflows (changes from H'0000
to H'FFFF)
When 0 is written to TCFU after reading TCFU = 1
When the TCNT value overflows (changes from H'FFFF
to H’0000)
In channel 4, when TCNT-4 is underflowed (H'0001 →
H'0000) in complementary PWM mode.
When 0 is written to TCFV after reading TCFV = 1
In channel 4, when DTC is activated by the TCIV
interrupt and the DISEL bit in DTMR of DTC is 0.

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