HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 15

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.8
9.9
9.10 On-chip Peripheral I/O Register Access ........................................................................... 148
9.11 Cycles in which Bus is not Released................................................................................. 148
9.12 CPU Operation when Program is In External Memory .................................................... 148
Section 10 Multi-Function Timer Pulse Unit (MTU) ........................................149
10.1 Features............................................................................................................................. 149
10.2 Input/Output Pins .............................................................................................................. 153
10.3 Register Descriptions ........................................................................................................ 154
10.4 Operation .......................................................................................................................... 194
10.5 Interrupts........................................................................................................................... 247
10.6 Operation Timing.............................................................................................................. 250
9.7.1
9.7.2
Bus Arbitration.................................................................................................................. 146
Memory Connection Example .......................................................................................... 147
10.3.1 Timer Control Register (TCR)............................................................................. 156
10.3.2 Timer Mode Register (TMDR) ............................................................................ 160
10.3.3 Timer I/O Control Register (TIOR) ..................................................................... 162
10.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 180
10.3.5 Timer Status Register (TSR)................................................................................ 182
10.3.6 Timer Counter (TCNT)........................................................................................ 185
10.3.7 Timer General Register (TGR) ............................................................................ 185
10.3.8 Timer Start Register (TSTR) ............................................................................... 186
10.3.9 Timer Synchro Register (TSYR) ......................................................................... 187
10.3.10 Timer Output Master Enable Register (TOER) ................................................... 188
10.3.11 Timer Output Control Register (TOCR).............................................................. 189
10.3.12 Timer Gate Control Register (TGCR) ................................................................. 191
10.3.13 Timer Subcounter (TCNTS) ................................................................................ 192
10.3.14 Timer Dead Time Data Register (TDDR)............................................................ 192
10.3.15 Timer Period Data Register (TCDR) ................................................................... 193
10.3.16 Timer Period Buffer Register (TCBR)................................................................. 193
10.3.17 Bus Master Interface............................................................................................ 193
10.4.1 Basic Functions.................................................................................................... 194
10.4.2 Synchronous Operation........................................................................................ 200
10.4.3 Buffer Operation .................................................................................................. 202
10.4.4 Cascaded Operation ............................................................................................. 206
10.4.5 PWM Modes ........................................................................................................ 207
10.4.6 Phase Counting Mode.......................................................................................... 212
10.4.7 Reset-Synchronized PWM Mode......................................................................... 218
10.4.8 Complementary PWM Mode............................................................................... 222
10.5.1 Interrupts and Priorities........................................................................................ 247
10.5.2 DTC Activation.................................................................................................... 249
10.5.3 A/D Converter Activation.................................................................................... 249
Prevention of Data Bus Conflicts......................................................................... 145
Simplification of Bus Cycle Start Detection........................................................ 145
Rev. 2.00, 09/04, page xiii of xl