HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 363

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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0
11.3.3
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows.
Note:
Bit
7
6
5
4 to 0
*
Bit Name
WOVF
RSTE
RSTS
Reset Control/Status Register (RSTCSR)
Only 0 can be written, for flag clearing.
Initial
Value
0
0
0
All 1
R/W
R/(W)*
R/W
R/W
R
Description
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode.
[Setting condition]
[Clearing condition]
Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows in watchdog timer
mode.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reset Select
Selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
0: Power-on reset
1: Manual reset
Reserved
These bits are always read as 1, and should only be
written with 1.
overflows
(Though other peripheral module registers are not
reset, TCNT and TCSR in WDT are reset)
Set when TCNT overflows in watchdog timer
mode
Cleared by reading WOVF, and then writing 0 to
WOVF
Rev. 2.00, 09/04, page 321 of 720

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