HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 581

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 18.1 Port A Data Register L (PADRL) Read/Write Operations
Bits 15 to 0:
18.2
Port B is an input/output port with the six pins shown in figure 18.2.
18.2.1
Port B is a 6-bit input/output port. Port B has the following register. For details on register
addresses and register states during each processing, refer to appendix A, Internal I/O Register.
• Port B data register (PBDR)
18.2.2
The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits
PB5DR to PB0DR correspond to pins PB5 to PB0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PBDR, that value is output
directly from the pin, and if PBDR is read, the register value is returned directly regardless of the
pin state.
PAIORL
0
1
Port B
Port B
Register Descriptions
Port B Data Register (PBDR)
Pin Function
General input
Other than
general input
General output
Other than
general output
PB5 (I/O) / IRQ3 (input) / POE3 (input) / CK (output)
PB4 (I/O) / IRQ2 (input) / POE2 (input) / SCK4 (I/O)
PB3 (I/O) / IRQ1 (input) / POE1 (input) / TXD4 (output)
PB2 (I/O) / IRQ0 (input) / POE0 (input) / RXD4 (input)
PB1 (I/O) / A17 (output) / HRxD1 (input) / SCK4 (I/O)
PB0 (I/O) / A16 (output) / HTxD1 (output)
Read
Pin state
Pin state
PADRL value
PADRL value
Figure 18.2 Port B
Write
Can write to PADRL, but it has no effect on pin
state
Can write to PADRL, but it has no effect on pin
state
Value written is output from pin
Can write to PADRL, but it has no effect on pin
state
Rev. 2.00, 09/04, page 539 of 720