HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 653

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.3
24.3.1
Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0,
the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the
CPU's internal registers are retained. Peripheral functions except the CPU do not stop.
In sleep mode, data should not be accessed by the DTC or AUD.
Clearing Sleep Mode: Sleep mode is cleared by the conditions below.
• Clearing by the power-on reset
• Clearing by the manual reset
• Clearing by the HSTBY pin
24.3.2
Transition to Software Standby Mode: A transition is made to software standby mode if the
SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In this mode, the CPU,
on-chip peripheral functions, and the oscillator, all stop.
However, the contents of the CPU's internal registers and on-chip RAM data are retained as long
as the specified voltage is supplied. There are two types of on-chip peripheral module registers;
ones which are initialized by software standby mode, and those not initialized by that mode. For
details, refer to appendix A.3, Register States in Each Operating Mode. The port high-impedance
bit (HIZ) in SBYCR sets the state of the I/O port either to "retained" or "high-impedance". For the
state of pins, refer to appendix B, Pin States. In software standby mode, the oscillator stops and
thus power consumption is significantly reduced.
When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven
high after the elapse of the specified reset input period, the CPU starts the reset exception
handling.
When an internal Power-on reset by WDT occurs, sleep mode is also cleared.
When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual
reset state and thus sleep mode is cleared.
When an internal manual reset by WDT occurs, sleep mode is also cleared.
When the HSTBY pin is driven low, the CPU shifts to hardware standby mode.
Operation
Sleep Mode
Software Standby Mode
Rev. 2.00, 09/04, page 611 of 720