HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 70

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Rev. 2.00, 09/04, page 28 of 720
Instruction Formats
md format
15
nd4 format
15
nmd format
15
d format
15
d12 format
15
nd8 format
15
i format
15
ni format
15
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
*
dddd
xxxx
nnnn
nnnn
xxxx
nnnn
xxxx
xxxx
In multiply-and-accumulate instructions, nnnn is the source register.
mmmm
mmmm
dddd
dddd
dddd
nnnn
i i i i
i i i i
dddd
dddd
dddd
dddd
dddd
dddd
i i i i
i i i i
0
0
0
0
0
0
0
0
Source
Operand
mmmmdddd:
Indirect register
with displacement
R0 (Direct register) nnnndddd:
mmmm: Direct
register
mmmmdddd:
Indirect register
with displacement
dddddddd: Indirect
GBR with
displacement
R0 (Direct register) dddddddd: Indirect
dddddddd: PC
relative with
displacement


dddddddd: PC
relative with
displacement
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Destination
Operand
R0 (Direct
register)
Indirect register
with displacement
nnnndddd: Indirect
register with
displacement
nnnn: Direct
register
R0 (Direct register) MOV.L
GBR with
displacement
R0 (Direct register) MOVA
dddddddd: PC
relative
dddddddddddd:
PC relative
nnnn: Direct
register
Indirect indexed
GBR
R0 (Direct register) AND

nnnn: Direct
register
Example
MOV.B
@(disp,Rn),R0
MOV.B
R0,@(disp,Rn)
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
@(disp,GBR),R0
MOV.L
R0,@(disp,GBR)
@(disp,PC),R0
BF
BRA
(label = disp
+ PC)
MOV.L
@(disp,PC),Rn
AND.B
#imm,@(R0,GBR)
TRAPA
ADD
label
label
#imm,R0
#imm
#imm,Rn