HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 523

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.8.9
If the transmit wait register (TXPR) is set during transfer of EOF for the message being
transmitted or received, normal transfer of the data may be inhibited.
• Conflict with EOF during message reception: The reception might not proceed normally
• Conflict with EOF during message transmission: The transmission might not proceed normally
The occurrence of the phenomena described above depends on the settings of the operating clock
and baud rate for the HCAN2, the number of transmission mailboxes set in the TXPR register, and
the number of times the mailboxes are accessed by the CPU after the TXPR register has been set.
Software Measure:
Program so that the TXPR bits are set by package to all the mailboxes that require transmission
wait until the transmission from all of the specified mailboxes and the reception from the CAN
bus are completed, confirm that the TXPR has been cleared and RXPR set to 1, then set the TXPR
again.
15.8.10 Limitation on Access to the Local Acceptance Filter Mask (LAFM)
Read access to the local acceptance filter mask register (LAFM) during message transmission may
damage the data in the register.
Software Measure: Program so that the LAFM register is only accessed in the configuration mode
(MCR0 = 1)
15.8.11 Notes on Using Auto Acknowledge Mode
In the Self Test by setting the TST4 bit (Auto Acknowledge Mode) in the master control register
(MCR) to 1, transmission can be performed but receiving the transmit data cannot be performed.
15.8.12 Notes on Usage of the Transmit Wait Cancel Register (TXCR)
• If a transmit wait cancel register (TXCR) setting to cancel transmission is made immediately
because the data received at the previous reception may not be stored at the reception of the
next SOF.
because the ID of the next data for transmission may have been damaged. Transmission will
proceed normally when the TXPR bits are set by package to all the mailboxes that require
transmission after all of the data for transmission have been transmitted.
after a transmission request (TXPR) has been issued at the SOF or during an intermission,
canceling of the message being prepared for transmission is not possible so that transmission
Cases when the Transmit Wait Register (TXPR) is Set during Transfer of EOF
Rev. 2.00, 09/04, page 481 of 720