HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 17

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Operation .......................................................................................................................... 322
11.5 Interrupts........................................................................................................................... 325
11.6 Usage Notes ...................................................................................................................... 325
Section 12 Serial Communication Interface (SCI) ............................................329
12.1 Features............................................................................................................................. 329
12.2 Input/Output Pins .............................................................................................................. 331
12.3 Register Descriptions ........................................................................................................ 332
12.4 Operation in Asynchronous Mode .................................................................................... 351
12.5 Multiprocessor Communication Function......................................................................... 362
11.3.1 Timer Counter (TCNT)........................................................................................ 319
11.3.2 Timer Control/Status Register (TCSR)................................................................ 319
11.3.3 Reset Control/Status Register (RSTCSR)............................................................ 321
11.4.1 Watchdog Timer Mode ........................................................................................ 322
11.4.2 Interval Timer Mode............................................................................................ 323
11.4.3 Clearing Software Standby Mode ........................................................................ 324
11.4.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 324
11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 325
11.6.1 Notes on Register Access..................................................................................... 325
11.6.2 TCNT Write and Increment Contention .............................................................. 327
11.6.3 Changing CKS2 to CKS0 Bit Values .................................................................. 327
11.6.4 Changing between Watchdog Timer/Interval Timer Modes................................ 327
11.6.5 System Reset by WDTOVF Signal...................................................................... 328
11.6.6 Internal Reset in Watchdog Timer Mode............................................................. 328
11.6.7 Manual Reset in Watchdog Timer Mode ............................................................. 328
11.6.8 Handling of WDTOVF pin .................................................................................. 328
12.3.1 Receive Shift Register (RSR) .............................................................................. 333
12.3.2 Receive Data Register (RDR) .............................................................................. 333
12.3.3 Transmit Shift Register (TSR) ............................................................................. 333
12.3.4 Transmit Data Register (TDR)............................................................................. 333
12.3.5 Serial Mode Register (SMR) ............................................................................... 334
12.3.6 Serial Control Register (SCR) ............................................................................. 335
12.3.7 Serial Status Register (SSR) ................................................................................ 337
12.3.8 Serial Direction Control Register (SDCR)........................................................... 340
12.3.9 Bit Rate Register (BRR) ...................................................................................... 340
12.4.1 Data Transfer Format........................................................................................... 351
12.4.2 Receive Data Sampling Timing and Reception Margin in
12.4.3 Clock.................................................................................................................... 354
12.4.4 SCI initialization (Asynchronous mode).............................................................. 355
12.4.5 Data transmission (Asynchronous mode) ............................................................ 356
12.4.6 Serial data reception (Asynchronous mode) ........................................................ 358
12.5.1 Multiprocessor Serial Data Transmission ............................................................ 364
Asynchronous Mode ............................................................................................ 353
Rev. 2.00, 09/04, page xv of xl