HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 124
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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6.4
6.4.1
There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral
modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and
16 the highest). Giving an interrupt a priority level of 0 masks it.
NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin
is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1)
to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt
mask level bits (I3 to I0) in the status register (SR) to level 15.
IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Set
the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register 1 (ICR1) and IRQ
edge select bit (IRQ0ES[1:0] to IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select
low level detection, falling edge detection, or rising edge detection for each pin. The priority level
can be set from 0 to 15 for each pin using the interrupt priority registers A (IPRA).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F to IRQ3F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for
IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to
confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to
IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request
detection results can be withdrawn.
In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block
diagram of this IRQ3 to IRQ0 interrupts.
Rev. 2.00, 09/04, page 82 of 720
Interrupt Sources
External Interrupts
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