HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 40

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Controller Area Network 2 (HCAN2)
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Section 16 Motor Management Timer (MMT)
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Section 17 Pin Function Controller (PFC)
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Table 17.7
Section 18 I/O Ports
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Section 19 Flash Memory (F-ZTAT Version)
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Section 22 High-Performance User Debugging Interface (H-UDI)
Table 22.1
Table 22.2
Section 23 Advanced User Debugger (AUD)
Table 23.1
Table 23.2
Rev. 2.00, 09/04, page xxxviii of xl
HCAN2 Pins ......................................................................................................... 410
Mailbox Configuration Bit Setting ....................................................................... 453
Message Data Area Configuration in TCT Bit Setting ......................................... 454
Limits on BCR Settable Values ............................................................................ 463
Setting Range for TSEG1 and TSEG2 in BCR..................................................... 464
HCAN2 Interrupt Sources .................................................................................... 477
Pin Configuration.................................................................................................. 485
Initial Values of TBRU to TBRW and Initial Output ........................................... 496
Relationship between A/D Conversion Start Timing and Operating Mode.......... 500
MMT Interrupt Sources ........................................................................................ 500
Pin Configuration.................................................................................................. 509
Multiplexed Pins (Port A)..................................................................................... 515
Multiplexed Pins (Port B) ..................................................................................... 516
Multiplexed Pins (Port D)..................................................................................... 516
SH7047 Multiplexed Pins (Port E) ....................................................................... 517
Multiplexed Pins (Port F) ..................................................................................... 518
Pin Functions in Each Mode (1) ........................................................................... 519
SH7047 Pin Functions in Each Mode (2) ............................................................. 522
Port A Data Register L (PADRL) Read/Write Operations ................................... 539
Port B Data Register (PBDR) Read/Write Operations ......................................... 540
Port D Data Register L (PDDRL) Read/Write Operations ................................... 542
Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations ... 545
Port F Data Register (PFDR) Read/Write Operations .......................................... 547
Differences between Boot Mode and User Program Mode .................................. 551
Pin Configuration.................................................................................................. 555
Setting On-Board Programming Modes ............................................................... 559
Boot Mode Operation ........................................................................................... 561
Peripheral Clock (Pφ) Frequencies for which Automatic
Adjustment of LSI Bit Rate is Possible ................................................................ 561
H-UDI Pins ........................................................................................................... 583
Serial Transfer Characteristics of H-UDI Registers.............................................. 584
AUD Pins.............................................................................................................. 594
Ready Flag Format ............................................................................................... 600