HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 183

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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9.6
A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct
connections.
9.6.1
External access bus cycles are performed in 2 states. Figure 9.3 shows the basic timing of external
space access.
During a read, irrespective of operand size, all bits (8 bits in this LSI) in the data bus width for the
access space (address) accessed by RD signal are fetched by the LSI.
During a write, the WRL (bits 7 to 0) signal indicates the byte location to be written.
Accessing External Space
Basic Timing
Figure 9.3 Basic Timing of External Space Access
Write
Read
Address
WRL
Data
Data
CS0
RD
CK
T1
T2
Rev. 2.00, 09/04, page 141 of 720

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